1. Field of the Invention
This invention relates to a semiconductor integrated circuit having an active clamping circuit for protecting a semiconductor element at an output stage from an overvoltage applied externally.
2. Description of the Related Art
A power IC having a transistor at the output stage (hereinafter referred to as "an output transistor"), a driving circuit and/or a controlling circuit for the transistor, and a protection circuit for the transistor, integrated on the same chip, is well known.
It is frequently the case that, a high voltage due to static electricity, a surge voltage induced in an induction load and, irregularity of the load, is supplied to an output terminal of this output transistor as an overvoltage. Therefore, various overvoltage protection circuits protecting the output transistor from these overvoltages have been devised
In recent years, the switching speed of the output transistor has become higher and higher. At a turn-off transition of the output transistor, a back electromotive force (voltage) is induced due to the inductance of the load circuit. The back electromotive voltage induced by turning off the current in the inductive load can cause breakdown of the output transistor, since the output transistor is in a high impedance state. Therefore, a countermeasure for this surge voltage has been required.
When a solenoid is used as the load of the output transistor, a back electromotive voltage induced by a process of turning the solenoid off is becoming a problem.
Therefore, a protection circuit which protects the output transistor from the surge voltage caused by this back electromotive voltage has become necessary.
FIG. 1 shows a protection circuit for protecting the output transistor. That is, FIG. 1 is one example of an overvoltage protection circuit employing an active clamping circuit in order to protect the output transistor Tr1 from the surge voltage induced by a turn-of-process of a solenoid. The solenoid 1 comprises an inductance component L1 and a resistance component R1, and one terminal thereof is connected to an alternator 3 and a battery 4 through an IGN-line 2, and the other terminal thereof is connected to an output terminal 12 of a power integrated circuit 40 (hereinafter referred to as "a power IC").
The power IC 40 has a transistor controller 13 of the output transistor merged in the same chip with the output transistor Tr1. The transistor controller 13 is driven by a control signal transferred from a CPU through an input terminal 11. The output transistor Tr1 is switched on and off by the transistor controller 13, whereby the solenoid 1, connected to an output terminal of the output transistor Tr1, is driven by the output current from the output transistor. In addition, a clamping circuit 41 and resistors R2 and R3 for protecting the output transistor Tr1 from the surge voltage being supplied from the output terminal 12, are integrated on power IC 40.
The clamping circuit 41 is constituted by a diode D1 and a Zener diode ZD3 connected in series, with the respective anode sides joined together. The input terminal 11 of the power IC 40 is connected to the input of the transistor controller 13 and the output of the transistor controller 13 is connected to the resistance R2, which has the other side thereof grounded. The output of the transistor controller 13 is also connected to the cathode side of the diode D1 of the clamping circuit 41 and to the resistor R3.
The other side of the resistor R3 is connected to a gate g1 of the output transistor Tr1. A drain d1 of the output transistor Tr1 is connected to the output terminal 12 and to the cathode side of the Zener diode ZD3 of the clamping circuit 41. A source s1 of the output transistor Tr1 is grounded.
By this circuit configuration, at the turning off of the output transistor Tr1, the surge voltage induced in the solenoid 1, connected as the load, is supplied to the drain d1 of the output transistor Tr1. The clamping circuit 41 is a protection circuit for preventing the output transistor Tr1 from being broken-down due to this surge voltage. That is, before the output transistor Tr1, being in an off-state, is broken-down, the Zener diode ZD3 of the clamping circuit 41 is conducted, whereby the potential of the gate g1 of the output transistor Tr1 is increased. Therefore, the output transistor Tr1 turns on, whereby the current, due to the surge voltage, flows from the drain d1 of the output transistor Tr1 toward the source s1. As described above, since the output transistor Tr1 turns-on, an excessive high voltage, or the surge voltage, is not supplied between the drain and the source, whereby the output transistor Tr1 is prevented from being broken-down.
At normal operation, the control signal from the transistor controller 13 for turning the output transistor Tr1 on, is transferred to the gate g1. The diode D1 is installed for breaking a current path, flowing from the gate g1 to the side of the drain d1 directly without passing through the output transistor Tr1, when the control signal is transferred to the gate g1.
Next, a detail operation in each portion of the power IC 40 is described using a timing chart in FIG. 2.
When a solenoid controlling signal "a", as shown in FIG. 2, is sent from a CPU 5, the transistor controller 13 sends a transistor controlling signal "b". The transistor controlling signal "b" supplies a gate voltage for turning the output transistor Tr1 to the on-state or the off-state.
At a timing t7 in FIG. 2, when the solenoid controlling signal "a" turns into a "high level", the transistor controlling signal "b" also turns into the "high level", whereby the output transistor Tr1 turns to the on-state. As a result, a drain current I.sub.d flowing between the drain and the source of the output transistor Tr1 flows in the solenoid 1 having the resistance component R1. At this point of time, when defining an on-resistance of the output transistor Tr1 as R.sub.on and a normal voltage of an IGN-line as V.sub.ign, a drain current I.sub.don can be represented by EQU I.sub.don =V.sub.ign /(R1+R.sub.on) (1).
Usually, since the on-resistance R.sub.on of the output transistor Tr1 and the resistance component R1 of the solenoid 1 are selected so as to be EQU R.sub.on &lt;&lt;R1 (2),
the drain current I.sub.don in the on-state of the output transistor Tr1 is considered to be EQU I.sub.don =V.sub.ign /R1 (3).
Since the drain current I.sub.don in the on-state of the output transistor Tr1 also is a current which flows in the solenoid 1, an energy Es stored in the solenoid 1 becomes at this time EQU Es=1/2.multidot.L1.multidot.(V.sub.ign /R1).sup.2 (4).
Next, at a timing t8 in FIG. 2, when the solenoid controlling signal "a" is switched from an on-signal to an off-signal, the transistor controlling signal "b" also turns to a "low level", whereby the output transistor Tr1 turns to the off-state. When the output transistor Tr1 turns to the off-state, a back electromotive voltage is induced in the solenoid 1, and this voltage is supplied to the output terminal 12 of the power IC 40 as the surge voltage.
This surge voltage is clamped by a Zener voltage V.sub.z 3 of the Zener diode ZD3, a forward voltage V.sub.d 1 of the diode D1 and a gate threshold voltage V.sub.gs (th) of the output transistor Tr1. Accordingly, a clamping voltage V.sub.c 4 becomes EQU V.sub.c 4=V.sub.z 3+V.sub.d 1+V.sub.gs (th) (5).
As shown in FIG. 2, a voltage V.sub.gs between the gate and the source of the output transistor Tr1 is reduced instantaneously at the timing t8 when the transistor controlling signal "b" turns to the "low level" and the output transistor Tr1 turns to the off-state. But immediately afterward, the clamping circuit 41 is conducted by the back electromotive voltage induced in the solenoid 1, whereby a positive voltage is supplied to the gate g1. And when the voltage supplied to the gate g1 exceeds the gate threshold voltage V.sub.gs (th), the output transistor Tr1 turns to the on-state again.
A voltage V.sub.ds between the drain and the source of the output transistor Tr1 is kept at the clamping voltage V.sub.c 4 of the surge voltage for a period from the timing t8 to a timing t9, during which the clamping circuit 41 is conducted. Then, the voltage V.sub.ds is kept at the IGN-line normal voltage V.sub.ign, from after the timing t9 at which the surge voltage disappears, so that clamping circuit 41 is not conducted.
Immediately after the solenoid controlling signal "a" is switched from an on-signal to an off-signal, a peak power value PP4 defined as the instantaneous value of a power P4 dissipated by the output transistor Tr1 is given by: (the clamping voltage V.sub.c 4).times.(the drain current I.sub.don). Then, from the formula (3) and the formula (5), ##EQU1## is obtained.
When defining the time which a surge energy E.sub.s is dissipated by the output transistor Tr1 as T4, a power loss P4.sub.s by the surge voltage becomes, from the formula (6), ##EQU2##
Since the power loss P4.sub.s and the surge energy Es are equal, the time T4 becomes ##EQU3##
That is to say, when the peak power value PP4, immediately after a solenoid current is cut off, is large, the time T4 is short. And when the peak power value PP4 is small, the time T4 is long.
Next, a range of the clamping voltage V.sub.c 4 is described using FIG. 3. As shown in FIG. 1, the IGN-line 2 is connected to the battery 4 and the alternator 3. Moreover, usually, the voltage of the battery 4 is supplied to the IGN-line 2. However, when the positive terminal of the battery 4 is disconnected by some reason, an overvoltage V.sub.a from the alternator 3, exceeding the IGN-line normal voltage V.sub.ign, is supplied to the IGN-line 2 directly.
By this overvoltage V.sub.a from the alternator 3, the clamping circuit 41 is conducted. If the output transistor Tr1 were turned on by the clamping circuit 41, the solenoid 1 would fail to function properly. Accordingly, while the output transistor Tr1 is in an off-state, a specific bias condition such that the output transistor Tr1 can not be turned on by this overvoltage V.sub.a from the alternator 3 is generally employed. Namely, the clamping voltage V.sub.c 4 is set so as to be EQU V.sub.c 4&gt;V.sub.a -V.sub.on, (9),
wherein V.sub.on is an on-voltage of the solenoid 1.
Moreover, if the clamping voltage V.sub.c 4 were higher than a breakdown voltage BV.sub.ds between the drain and the source of the output transistor Tr1, the output transistor Tr1 would be destroyed by the surge voltage induced in the solenoid 1. Therefore, the clamping voltage V.sub.c 4 should be lower than the breakdown voltage BV.sub.ds of the output transistor Tr1. That is, the clamping voltage V.sub.c 4 is set so as to be EQU V.sub.c 4&lt;BV.sub.ds (10).
Accordingly, from the formula (9) and the formula (10), the range of the clamping voltage V.sub.c 4 becomes EQU V.sub.a -V.sub.on &lt;V.sub.c 4&lt;BV.sub.ds (11).
Based on the above description, using the formula (5) and the formula (11), by setting the forward voltage V.sub.d 1 of the diode D1 and the Zener voltage V.sub.z 3 of the Zener diode ZD3 so as to be EQU V.sub.a -V.sub.on &lt;V.sub.z 3+V.sub.d 1+V.sub.gs (th)&lt;BV.sub.ds (12),
the clamping circuit 41 can protect the output transistor Tr1 from destruction due to the overvoltage.